Regviz

Cypress Semiconductor /psoc63 /CPUSS /CM0_INT_CTL5

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CM0_INT_CTL5

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Cypress Semiconductor/psoc63/CPUSS/CM0_INT_CTL5#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MUX0_SEL0MUX1_SEL0MUX2_SEL0MUX3_SEL

Description

CM0+ interrupt control 5

Fields

MUX0_SEL

System interrupt select for CPU interrupt source 20.
MUX1_SEL

System interrupt select for CPU interrupt source 21.
MUX2_SEL

System interrupt select for CPU interrupt source 22.
MUX3_SEL

System interrupt select for CPU interrupt source 23.

Links

()

Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data